Multi-function microprocessor wait state mechanism using external control line
US5732250A · kind A · utility
52Cited by
4References
20Claims
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Key dates
| Filing date | Jan 20, 1997 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Jan 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4213
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wait state mechanism for lengthening a microprocessor's bus cycle to allow data transfers between slower off-chip devices. A microprocessor is responsive to a bus control signal generated by external programmable logic which instructs the microprocessor to insert wait states of varying number depending on the component involved in a bus transaction. The microprocessor receives only a single input from the programmable logic and varies its bus cycle length accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.