Microprocessor burst mode with external system memory
US5732406A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1992 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Sep 23, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcomputer architecture and method allows for high processing speeds. A microprocessor constitutes the central processing unit. The microprocessor comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit and the system memory communicate by way of a high speed host bus. The system memory is comprised of multiple buses and is capable of delivering data to the microprocessor in a burst mode at high speeds. A memory controller addresses data locations within the system memory upon receipt of a first host address from the microprocessor. Accordingly, the microprocessor can access data in the system memory at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.