Dual phase-locked loop clock synthesizer
US5734301A · kind A · utility
28Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 1996 |
| Grant date | Mar 31, 1998 |
| Priority date | — |
| Expiry date | Aug 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual phase-locked loop (PLL) clock synthesizer is disclosed for generating clock signal in synchronization with the data input signal received over a network environment. The dual PLL clock synthesizer is suitable for processing data streams of any bit sequence without data error caused by interference due to clock signal jittering phenomena. The dual PLL clock synthesizer is particularly suitable for application to high-speed Ethernet network environment such as for decoding to obtain the original data conveyed over the network through selected encoding scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.