Residual charge elimination for a memory device
US5734608A · kind A · utility
1Cited by
4References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 1995 |
| Grant date | Mar 31, 1998 |
| Priority date | — |
| Expiry date | Dec 29, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method is provided for addressing memory cells in a memory device, including two series connected select gates having a node between them. A switching element is connected between the node and a ground voltage. A control signal is applied to a control input of the switching element to render it conductive while both of the select gates are non-conductive, so as to eliminate charge stored at a node between the two select gates. A particular application to an addressing circuit for use in a flash EPROM memory device is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.