Method and apparatus for extracting a gate modeled circuit from a fet modeled circuit
US5734798A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 1995 |
| Grant date | Mar 31, 1998 |
| Priority date | — |
| Expiry date | Dec 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of extracting a gate model from a fet model using a computer implemented expert system apparatus to perform the steps of recognizing power, ground and clock signals; recognizing inverters; recognizing and preserving all logic signals of the fet modeled circuit; building one or more structurally based boolean partial trees for each of the recognized logic signals; heuristically pruning the one or more boolean trees; and building logic equations from the one or more boolean partial trees. The expert system apparatus comprises a fet modeled input netlist, an inference engine, a rule base, a user input, and a gate modeled output netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.