Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices
US5734847A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1995 |
| Grant date | Mar 31, 1998 |
| Priority date | — |
| Expiry date | Jun 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for creating an intelligent input/output subsystems which includes a local processor coupled to a local system bus; a local memory controller coupled to the local system bus that enables access to a memory from the local system bus; a bus bridge having a first bus interface coupled to a first component bus; a second bus interface coupled to a second component bus, the bus bridge including means for creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; and address translation means coupled to the local system bus and the bus bridge for translating addresses between the local system bus and the second component bus. A method for creating private devices comprising the steps of configuring the bus bridge to disable the assertion by the first component of a component select signal on the second component bus; creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; translating the private address to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.