Fast instruction decoding in a pipeline processor
US5734854A · kind A · utility
3Cited by
18References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 6, 1997 |
| Grant date | Mar 31, 1998 |
| Priority date | — |
| Expiry date | Jan 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer where instructions are fetched in segments and where segments of an instruction are assembled before execution is initiated, processing of instructions is accelerated by examining segments of the instructions they are fetched. The information obtained from such examination is then used to shorten the decoding step for the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.