Integrating multi-modal synchronous interrupt handlers for computer system
US5734910A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1995 |
| Grant date | Mar 31, 1998 |
| Priority date | — |
| Expiry date | Dec 22, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/463
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous interrupt handler for a processing system executing multiple modes of operation employs a minimum number of lines of interrupt handler code written to execute at the "zeroth" level, is combined with a virtualized interrupt vector table. An identical zeroeth level handler is inserted at each of the processor's interrupt vector entry pints. These short code sequences are the first to gain control following an interrupt. They are handwritten in the platform's native instruction set to be mode-independent. For example, if the platform's processor does not alter the "endianness" of the machine state following an interrupt, the "zeroeth level" code must be written for endian neutrality; likewise, for 32/64-bit mode, etc. For each mode of operation, there is created a Virtualized Vector Table to represent the proper interrupt handlers for each physical interrupt level. Each task data structure, implicitly reflecting its unique mode of operation, contains a pointer to its virtualized vector table. The zeroeth-level handlers then extract the virtualized vector table reference for their own interrupt level and indirectly pass control to the preloaded table value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.