Method and apparatus for fast self-destruction of a CMOS integrated circuit
US5736777A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1995 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Dec 29, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for fast electronic self-destruction of a CMOS integrated circuit. The present invention electrically destroys devices containing semiconductor components, securing the components from inspection by detecting the initiation of an attempt to inspect the component and, responsive thereto, electrically destroying the component. In some embodiments of the present invention, a switcheable pad having a destruct state and an operating state is connected to a well or to the substrate of the semiconductor device. When in destruct state, the switcheable pad drives the voltage of the well or substrate to a voltage that induces latch-up of the semiconductor device, allowing very large currents to flow through active or passive elements fabricated on the surface of the semiconductor device. In some embodiments, a fusible link having an open state and a closed state connects the switcheable pad to one power supply, so that when the switcheable pad is switched to the destruct state, the fusible link opens, thereby redirecting current through the parasitic PNPN junction of the semiconductor device, thus inducing large latch-up currents through the cell's fusible link and cau…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.