Patent · US Expired

Complementary clock systems

US5736882A · kind A · utility

13Cited by

4References

19Claims

0Family size

Assignee

Deutsche ITT Industries, GmbH · DE

Inventor

Franz-Otto Witte · Landsberg am Lech, DE

Key dates

Filing date	Dec 9, 1996
Grant date	Apr 7, 1998
Priority date	—
Expiry date	Dec 9, 2016

Classification

Technology area (CPC H)Electricity
CPC primaryH03K17/162
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A complementary clock system is disclosed for producing antiphase clock signals. The system includes a clock generator for producing a first clock signal (t3) and a second clock signal (t4). A first and second driver stage coupled to the clock generator for driving respective clock lines having a capacitive load that corresponds to a first load capacitance and a second load capacitance, respectively. A switchable current path coupled between the first and second clock lines which contains a gating circuit and at least one inductive element. The gating circuit being in a conducting state essentially during the switching intervals (ti) of the first and second clock signals (t3, t4).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.