Word line selection circuit for static random access memory
US5737275A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1996 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Mar 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory device disclosed has a boost circuit, a word drive circuit and a row decoder, and includes a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor, and a second N-channel MOS transistor. The first P-channel MOS transistor and the second P-channel MOS transistor have drains and gates cross-connected and each source and a substrate connected to an output terminal of the boost circuit. The first N-channel MOS transistor has a drain connected to the drain of the first P-channel MOS transistor, a source connected to a ground terminal, and a gate connected to an output terminal of the row decoder. The second N-channel MOS transistor has a source connected to the output terminal of the row decoder, a drain connected to the drain of the second P-channel MOS transistor, and a gate receiving one of a power supply voltage and a control signal. The gate of the N-channel word driver can be driven directly from the row decoder whereby the select and non-select ratio is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.