Method and apparatus for correlating logic analyzer state capture data with associated application data structures
US5737520A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1996 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Sep 3, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/322
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and associated apparatus for analyzing and presenting captured state logic data including memory accesses by an intelligent I/O interface device and an attached computer system. The data analysis and display of the present invention aids an engineer in locating data corruption failures in a system. The heuristic analysis of the methods of the present invention locate and identify buffers accessed within the captured state logic data and buffer descriptors accessed within the captured state logic data despite the time dispersion thereof. The buffers and buffer descriptors located and identified within the captured state logic data are displayed on a computer display screen in a manner to more effectively assist an engineer in locating a root cause of data corruption than was possible with prior methods devoid of the analysis of the present invention. In particular, the display visually identifies buffers regardless of the state/time dispersion in the original captured state logic data and distinguishes read access from write access thereto. The display includes indicia used to associate a located and identified buffer descriptor with the identified buffer to which it refers.…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.