System bus with separate address and data bus protocols
US5737546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1996 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Dec 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4213
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. In particular, the timing of data transactions and the rate at which data transactions occur on the data bus is independent of the timi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.