Data processing system having a memory with both a high speed operating mode and a low power operating mode and method therefor
US5737566A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1993 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Dec 20, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system having a memory with a low power operating mode and a method of operation is described. An static random access memory (SRAM) (18) having a low power operating mode is provided for a data processing system (10). A programmable control bit is used for switching the SRAM (18) from a one clock cycle operating mode to a two clock cycle, or low power, operating mode. Initially, during the two cycle operating mode, only a bus interface unit (41) is active. During the first cycle, an address is compared to determine if the address is a valid address. If the address is valid, address decoders (42) are enabled, and a data transfer is completed on the second clock cycle. If the address is not valid, the address decoders (42) remain disabled and memory array (43) remains in a quiescent state consuming minimum power. During one cycle mode, the SRAM (18) decodes every address in order to respond in one clock cycle to a valid address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.