Multiport high speed memory having contention arbitration capability without standby delay
US5737569A · kind A · utility
20Cited by
11References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1996 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Mar 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arbitration circuit and method for a multiport high speed memory in a computer microprocessor. A plurality of addresses are provided to a plurality of ports. The addresses are decoded in a plurality of decoders. The decoded output lines are compared in a comparison circuitry to determine if one or more of the ports is requesting access to the same memory line, and a comparison bit indicative of a match is outputted. If asserted, the comparison bit disables a line driver so that only one of the wordlines in a particular memory line is driven at any one time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.