Data transfer system and method including tuning of a sampling clock used for latching data
US5737589A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1994 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Sep 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.