Power-on reset control circuit
US5737612A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1994 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-on reset control circuit and associated method for deactivating a global power-on-reset signal based on whether circuitry, critical to correct functionality of an electronic system employing the power-on reset, is functioning correctly. The power-on reset control circuit comprises a control emulation circuit for transmitting a control signal through a first control line to indicate that the circuitry is operating correctly. The power-on reset control circuit further comprises a control verification circuit, coupled to the control emulation circuit through the first control line, for deactivating the global power-on reset signal upon receiving an active local power-on reset signal indicating that the power source is providing a voltage at an operating threshold level and the active control signal from the control emulation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.