Method of forming a semiconductor device having high and low resistance polysilicon
US5739059A · kind A · utility
4Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 1997 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | May 5, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/914
Abstract
The present invention is a method of manufacturing a high/low resistance on a mix-mode product. The method includes forming a polysilicon layer over a wafer. A blanket ion implantation is performed to implant ions into the entire polysilicon layer. The polysilicon layer is then separated into a high resistance area and a low resistance area. The low resistance area top surface is raised higher than the high resistance area. A photoresist is then formed on the polysilicon areas. The photoresist is subsequently etched back to the top surface of the low resistance areas. A second implant is done on the low resistance area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.