Non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture and programming method for the same
US5739568A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 1995 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Nov 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5612
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An object of the present invention is to contribute to increase of storage capacity of a memory. A non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture. The memory has a storage cell transistor which comprises source 2 and drain 3 being formed in a semiconductor substrate 1 distantly from each other. The storage cell transistor, furthermore comprises a single first floating gate 4A being laid between the source and drain above the semiconductor substrate, and a plurality of second floating gates 4B.sub.1 -4B.sub.n which are distant from each other and face the first floating gate. Since the second floating gates respectively store carrier corresponding to data bits and the first floating gate determines a threshold value of drain current in accordance with sum amount of carrier stored in all of the second floating gates, two or more bits data can be saved per one storage cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.