Semiconductor memory having improved data bus arrangement
US5740120A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 4, 1996 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Jan 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory including first, second, and third data busses, and first and second memory cell arrays arranged among the first, second, and third data busses. During operation of the semiconductor memory, a first, a second, and a third switch circuit selectively couple the first, second, and third data busses to a fourth and a fifth data bus. Additionally, there is provided first and second buffer circuits, which are respectively coupled to the fourth and the fifth data busses, and a sixth data bus, which is commonly coupled to the first and second buffer circuits. A control circuit is used to control the operation of the switch circuits. In a preferred embodiment, the semiconductor memory has an equal number of buffer circuits and memory cell arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.