Dual differential and binary data transmission arrangement
US5740201A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data transmission arrangement for transmitting data between integrated circuit chips in a computer comprises a driver circuit having inputs connected to two discrete data bits. The driver circuit converts the states of the two data bits to one of four possible output voltage levels on each of two data transmission conductors. A receiver circuit connected to the data transmission conductors converge the multi-level signals on the pair of transmission conductors into binary output signals for use in a receiving circuit chip. The driver circuit and receiver circuit are balanced circuits and symmetrically arranged such that essentially the same magnitude of current is drawn from the power bus independent of the value of the signal being transmitted, thereby eliminating Delta-I noise typically occurring on a power bus when binary data is transmitted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.