Dynamic arbitration priority
US5740383A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1995 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Dec 22, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arbitration controller that temporarily raises the priority of a graphic device's HWM request above that of the BitBLT engine while that device's LWM request is being served. In this manner, the BitBLT engine cannot interrupt the transfer of data to the graphics device. Each device capable of issuing memory access requests is categorized into one of four classes. The LWM requests are the highest priority requests, followed by CPU memory access requests, then BitBLT engine requests, and finally by HWM requests. When a LWM request is granted, the requesting device's HWM request is elevated to a priority between the CPU and the BitBLT engine. Once the LWM request is complete, the HWM request is served until either it completes, the CPU issues a memory access request, or another LWM request occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.