Low load host/PCI bus bridge
US5740385A · kind A · utility
16Cited by
6References
53Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1994 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Dec 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.