Digital signal processor with on-chip select decoder and wait state generator
US5740404A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 1993 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Sep 27, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processor (DSP) provides an improvement in the interfacing and sharing of external memory devices. Specifically, the digital signal processor is provided with a parallel interface for communicating with external memory devices, a chip select decoder located on-chip for selectably enabling external memory devices, and a wait status controller for holding processor operation until the selected memory device is ready. The memory architecture is configurable for internal or external wait state generation and memory sharing with other DSPs so that a plurality of varying speed memory devices may be accessed. The chip select decoder includes a programmable register for storing a mode configuration word for defining a plurality of external memory configurations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.