Static clock generator
US5740410A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1995 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Dec 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes clock circuitry that statically multiplies/divides a stimulus signal which can then be removed while a resultant product clock is still generated, A cascaded--dual tap delay line is employed having a single phase inversion which is looped back and logically ORed with the first edge of the stimulus signal to induce oscillation. A multiplier/divisor control signal adjusts the "N" times multiplication by disabling the loop after the desired number of pulses is achieved within the period of the stimulus signal. 1/M multiplication is achieved by disabling the loop from oscillating for M stimulus clocks. Multiple frequencies can be dynamically realized on-the-fly without resynchronization by combining delayed clock pulses with a multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.