Data demultiplexer
US5742361A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1996 |
| Grant date | Apr 21, 1998 |
| Priority date | — |
| Expiry date | Nov 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/44016
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data demultiplexer includes a write controller, a memory, an analyzing processing unit, and transfer control units. The write controller writes packets which have arrived thereat into the memory in the order of arrival and sends the write information to the analyzing processing unit. The analyzing processing unit analyzes packets in the order of arrival on the basis of the write information and sends only the result of analysis to the transfer control units. On the basis of the result of analysis, the transfer control units send data read from the memory in the order of packet arrival to the decoder. A data demultiplexer capable of reducing the processing in the analyzing processing unit can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.