Multi-port random access memory
US5742557A · kind A · utility
51Cited by
4References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 19, 1996 |
| Grant date | Apr 21, 1998 |
| Priority date | — |
| Expiry date | Sep 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.