Non-volatile semiconductor memory
US5742615A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 1996 |
| Grant date | Apr 21, 1998 |
| Priority date | — |
| Expiry date | Jun 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to shorten initialization time, a flash type non-volatile semiconductor memory of the invention comprises a line decoder (2) for selecting all of word lines (WL1 to WLm), a word line voltage generator (3) for generating various voltage, a column decoder (4) for selecting or not selecting all of digit lines (DL1 to DLn). Erase pulse impression process is performed by supplying a positive first word line voltage to all the word lines (WL1 to WLm) selected, and an erase voltage (Vs) to a source line, leaving all the digit line floating. All of memory-cell-transistors (MC11 to MCmn) are erased by infusing hot carriers in their floating gates by way of avalanche breakdown caused between their sources and substrates. Depression discrimination is performed with a sense amplifier (8) by selecting all digit lines (DL1 to DLn) and supplying all word lines (WL1 to WLm) with a second word line voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.