Mesh interconnected array in a fault-tolerant computer system
US5742753A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1996 |
| Grant date | Apr 21, 1998 |
| Priority date | — |
| Expiry date | Jun 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/187
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bus interface units (BIUs)(54) perform fault detection, identification, and reconfiguration for all information transfers between redundant central processing units (CPUs)(56) and memory or input/output (I/O)(57A-C) in a mesh interconnected array of a highly reliable fault-tolerant computer system. Errors are detected by self-checking within the BIUs, signal parity checks by the BIUs, cross channel comparisons, and mesh transaction assessments. Fault identification and mesh reconfiguration for the mesh is performed such that no faulty unit remains active in decision making after reconfiguration, and the number of good units isolated during reconfiguration is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.