Method and apparatus for synchronizing multiple clocks
US5742799A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1997 |
| Grant date | Apr 21, 1998 |
| Priority date | — |
| Expiry date | Feb 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for synchronizing multiple busses having different cycle times in a data processing system (10). The present invention synchronizes multiple clocks having different phase and frequencies without redundant use of phase lock loop units. An initial unit (7) receives an external system clock having an initial phase and frequency. An internal clock (112) is generated which is a phase and frequency adjusted derivation of the system clock. From this internal clock (112) a global clock (101) for use within the data processor (10) is generated. A second unit (9) receives the internal clock (112) and performs phase adjustment to provide a peripheral clock (114). The provision of the internal clock (112) detaches the dependency of peripheral clock (114) generation from the global clock (101), while maintaining a phase relationship with the global clock (101). In one embodiment, the present invention is implemented without the costly use of multiple phase lock loops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.