Enhanced power-on-reset/low voltage detection circuit
US5744990A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1995 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Nov 8, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comprehensive power-on-reset (POR) and low voltage detection circuit combines a Power Supply Voltage Level Detection (PSVLD) circuit with an Enhanced Retriggering (ER) circuit. The PSVLD circuit establishes lower and upper thresholds of the desired operating voltage range, and provide initial POR triggering and retriggering when the supply voltage is within the desired range. The ER circuit senses a predetermined amount of drop in the power supply voltage being monitored, and generates an independent pulse at the POR node whenever such a drop occurs. Total DC current is limited to less than 2.5 microamps, while power supply voltages can be monitored for stability over the range of 2.5 to 5.5 volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.