Gain calibration circuitry for an analog to digital converter
US5745060A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Feb 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/456
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method, and apparatus, for calibrating a delta sigma modulator. The delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. During the calibration mode, a feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle and an input signal section samples a calibration signal and transfers packets of charge corresponding to a portion of the calibration signal to the integrating capacitor in each modulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thus reducing idle-tones.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.