Arrangement for the summation of products of signals
US5745063A · kind A · utility
6Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1997 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Jun 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06J1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a circuit at least one of the signals (ut! or it!) is transmitted to a signal input of a sigma-delta modulator operated at a first clock frequency (1/T.sub.S) the output of which is connected to at least one of two signal inputs of a multiplication/addition element (3). The arrangement is used for example in electricity counters and makes it possible to calculate sums of products by means of simple shift and algebraic adding operations while maintaining closely the precision achievable with a classic multiplication. The arrangement is especially advantageous if the multiplications are done on a semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.