Time multiplexed addressing circuitry
US5745088A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Jun 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An array of individual elements (10) having reduced control circuitry as compared to existing devices. Sets of elements (11) share a memory cell (12), such that each memory cell (12) has the same fanout as other memory cells (12). Each element (11) in a set is switched to an on or off state via a reset line (13) that is separate from that of the other elements (11) in that set. Data is loaded in split bit-frames during a set time period, such that each split bit-frame contains only the data for elements (11) on one reset line (13). Thus, the same memory cell (12) can be used to deliver data to all elements (11) in its fanout because only one element (11) in the fanout is switched at a time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.