Pipelined architecture for patterned halftone generation
US5745249A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Dec 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/4055
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a super-scalar method and apparatus for the generation of halftone dot patterns in an image processing system. The super-scalar design employs at least one block of memory for the storage of at least one predetermined halftone dot pattern across a plurality of unique locations therein, and a sequencer for producing an index into said memory as a function of the position of the pixel along a scan line and the halftone dot characteristics. Also included is addressing circuitry for memory access control, to combine the index produced by said sequencer and a pixel value for the pixel to produce a memory address, the memory address being thereby employed to access one of said locations in memory and to cause said memory to output a signal representative of a portion of the halftone dot pattern stored at the unique addressed location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.