Integrated circuit system having reference cells for improving the reading of storage cells
US5745414A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Nov 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is an improvement in an analog storage device having a row of EEPROM cells. The improvement includes providing a reference EEPROM cell having first and second transistors connected in series, with a gate of the first transistor connected to a clear input line and a gate of the second transistor connected to a select input line. The improvement further includes providing a comparator having first and second inputs with the first input connected to a source of the second transistor and a second input connected to a reference voltage line and with an output of the comparator connected to the gate of the first transistor, wherein the gate of the first transistor is connected to gates of first transistors of each of the row of EEPROM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.