High capacity ATM switch
US5745486A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1995 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Oct 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An ATM switch architecture expandable to multi-terabits/s uses data transfer in a heterogeneous burst of a constant length. It employs rotators connecting stages in a three-stage switch configuration. In one embodiment, the cells are sorted at ingress and a matching process is performed between the first and middle stages. The switch is simple to control and has high performance at both the call and cell levels. It also meets the basic requirements that cells be delivered in the proper order, and that the rate of any individual connection be as high as the inlet-port rate. With a small internal expansion, the switch is non-blocking in the sense that any bit-rate acceptable to both the inlet and outlet ports will be guaranteed a path through the core. This feature is particularly useful in services which may require frequent bit-rate change during the connection time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.