Error correcting decoder
US5745506A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 25, 1995 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | May 25, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0052
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An error correcting decoder includes a flag memory (20) which stores a flag indicative of a success of an error correction for a bit. When a column direction error correction is to be performed, if a flag for a bit indicates a success, no error correction is performed for the bit. That is, an output of a majority logic circuit (78) is forcedly made invalid. In performing the column direction error correction, if the number of success packets in a first-time row direction error correction is smaller than a predetermined value and if the number of bits corrected by the column direction error correction becomes equal to or larger than a predetermined number, it is deemed as that the column direction error correction is unsuccessful. In performing a second-time row direction error correction, when a threshold value is equal to or larger than a predetermined value, the majority logic circuit determines with referring to a result of the column direction error correction, but without referring to the result when the threshold value is smaller than the predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.