System for detecting frame/burst synchronization and channel error using cyclic code
US5745510A · kind A · utility
5Cited by
13References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1995 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Jun 29, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/048
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for detecting a frame/burst synchronization and a channel error using a cyclic code (n,k). A received block of 2n-k bits is divided into a head block including first n-k bits of the received block, a middle block including the subsequent k bits of the received block and a tail block including last n-k bits of the received block. Head and tail syndromes are obtained on the basis of the divided head, middle and tail blocks. The frame/burst synchronization and the presence of the channel error are detected on the basis of the obtained head and tail syndromes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.