Partitioned addressing apparatus for vector/scalar registers
US5745721A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scalar/vector processor capable of concurrent scaler and vector operations includes scalar resources to process scalar instructions, and vector resources adapted to be operated concurrently with the scalar resources and with one another to process vector instructions. The scalar resources include scalar registers, and the vector resources include vector registers. Decoding means decodes each of a number of address fields. Each field represents a register address to access alternatively one of the scalar registers or one of the vector registers depending on a value of the register address being above or below a selected moveable address value within a range of addresses encompassed by the address field.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.