Parallel instruction execution with operand availability check during execution
US5745725A · kind A · utility
12Cited by
6References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 12, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Jul 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A succession of instructions are distributed between a plurality of multistage execution paths in a computer system. Each instruction is given a tag to identify the position of the instruction in the sequence and the execution paths of both that instruction and the preceding instruction. On entering an instruction in one execution path, register values are transferred from registers in a path executing a preceding instruction prior to completion of execution of that preceding instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.