Dual channel FIFO circuit with a single ported SRAM
US5745731A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1996 |
| Grant date | Apr 28, 1998 |
| Priority date | — |
| Expiry date | Mar 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with the present invention, there is provided a dual channel FIFO circuit to perform bidirectional data transfer under the control of a host computer between a host interface and a small computer system interface, comprising: a first multiplexing means for selecting one of the data from said host interface and the data from said small computer system interface; a single ported SRAM for storing the selected data by said first multiplexing means and outputting the data, which are indicated by pointers, according to the requests from said host interface or said small computer system interface; a second multiplexing means for selecting one of the data from said single ported SRAM and the data from said small computer system interface; a first staging memory means for storing the data to be outputted to said host interface; and a second staging memory means for storing the selected data by said second multiplexing means and transferring them to said second multiplexing means and said small computer system interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.