Semiconductor device with reduced breakdown voltage between the gate electrode and semiconductor surface
US5747851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A concave type DMOS transistor structure can attain improvement in a life-time of a gate insulating film. An initial groove portion is thermally oxidized with a silicon nitride film as a mask. A LOCOS oxide film is formed by this oxidation; concurrently, a U-groove is formed due to the erosion of the surface of an epitaxial layer by the LOCOS oxide film, and moreover the configuration of the groove is fixed. At this time, an inlet corner portion of the initial groove formed by chemical dry etching remains as a curving portion at a sidewall surface of the groove. Thereafter, a gate insulating film is formed, but thickness of the gate insulating film is controlled to be thicker on a groove inlet-portion side than on a groove bottom-portion side, with the curving portion as the boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.