Overload protection circuit for MOS power drivers

US5747975A · kind A · utility

Assignee

• SGS-Thomson Microelectronics S.A. · IT

Inventors

• Francesco Colandrea · Kellinghusen, DE
• Vanni Poletto · Trino, IT

Key dates

• Filing date: Mar 21, 1995
• Grant date: May 5, 1998
• Expiry date: Mar 21, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K17/0822
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The circuit includes two regulating loops connected in parallel to each other. A slow regulating loop presents a lower first intervention threshold, and a fast regulating loop has a higher second intervention threshold. The slow regulating loop is low-gain and frequency-stable for accurately controlling the maximum value of the current supplied by the driver in the event of slow overloads or transient states. In the event of rapid overloads, the current supply increases rapidly and the fast regulating loop is turned on to rapidly discharge the parasitic capacitance of the driver.