Data transfer system for an integrated circuit, capable of shortening a data transfer cycle
US5748018A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 1997 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Jan 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a data transfer system for use in an integrated circuit, a data output circuit comprises a D-FF for latching data to be transferred, in synchronism with an external clock signal, an output buffer receiving and outputting the data latched in the D-FF, and another output buffer receiving the external clock signal for outputting a delayed clock signal which is delayed from the external clock signal by a delay amount of the D-FF. On the other hand, a data input circuit including a first D-FF for receiving the data to be transferred outputted from the D-FF of the data output circuit, in synchronism with the delayed clock signal supplied from the D-FF of the data output circuit, and a second D-FF for fetching the data received in the first D-FF, in synchronism with the external clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.