Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit
US5748025A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Mar 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for providing a high voltage to a node of a low voltage tolerant CMOS integrated circuit process. In one embodiment, a pull up circuit is coupled between a high voltage source and the node and a pull down circuit is coupled between the node and a second voltage. The pull up circuit is configured to pull the voltage at the node to a high voltage while the pull down circuit is configured to the voltage at the node to a lower voltage. The pull down circuit includes a pair of series coupled n-channel transistors coupled between the node and the second voltage. The n-channel transistor connected to the node is a special n-channel transistor with a drain to substrate junction breakdown that is greater than the drain to substrate junction breakdown voltage of other ordinary n-channel transistors in the process. The special n-channel transistor is manufactured in an ordinary state-of-the-art CMOS integrated circuit process without adding any costly process steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.