High speed comparator with programmable reference
US5748071A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Nov 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system rapidly dynamic values (B) on a bus (12) to a programmable but thereafter fixed reference value (C). The system includes first leads (33) coupled to a comparison means (35), second leads (13) coupled to the bus (12) and third leads (34, 36) coupled to sources of potential (GND, VCC) related to logical HIGH and LOW of the fixed reference value (C). The leads (33, 13, 34, 36) are coupled in one or more programmable connection cell (32). Connections (471) or disconnections (461) are made between the leads (33, 13, 34, 36) so that the dynamic values (B) and the appropriate logical HIGH and logical LOW values are presented to the correct inputs of the comparison means (35). The programmable connections cells (32) invert the reference value (C) to (C) for coupling to the comparator (35). The system replaces a level of conventional decode logic (16) by the programmable interconnections (47), thereby reducing delay time, using fewer devices and occupying less circuit area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.