Low power logic minimization for electrical circuits
US5748490A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1995 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Oct 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process (601-611) and implementing computer system (13) for selecting a specific logic circuit among a group of otherwise acceptable alternative circuits, as represented by prime implicant terms (607), includes determining and assigning a power consumption factor (609) to each of the alternative logic circuit implementations. In the disclosed example, the probability of switching logic states (313, 513) is determined and used as a measure of the power consumption factor associated with each of the acceptable and valid prime implicant solutions for a given logic function. From a group of acceptable prime implicant solutions, the power optimum solution is chosen (611) which has been determined to be the most likely to consume the least amount of power in implementing the desired logic function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.