Apparatus and method for reducing test time of the data retention parameter in a dynamic random access memory
US5748544A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 1997 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Feb 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a dynamic random access memory device, the time required for implementation of memory cell data retention time testing procedures can be reduced by changing the voltage level(s) applied to the components of the storage cell when compared to the voltages applied during the typical memory cell operation. By changing the voltage(s) applied to the components, the difference in the bitlines detected by the sense amplifier will be reduced. Because to the reduced bitline voltage difference, the decay of the charge on the storage cell causes a reduction in the data retention time. The data retention time is reduced in manner related to the typical memory cell operation. The altered voltage(s) can be applied to the storage cell bitlines and/or to the storage cell dummy capacitances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.