Semiconductor memory device having extended margin in latching input signal
US5748553A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Sep 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes an internal clock signal generating section for generating an internal clock signal from an external clock signal. A latch section includes an address latching circuit for latching an inputted address, a command latching circuit for latching an inputted command and a write data latching circuit for latching an inputted write data. A state setting section controls the address latching circuit, the command latching circuit and the write data latching circuit based on an address key latched by the address latching circuit and a mode setting command latched by the command latching circuit such that a time difference is selectively extended between a first timing of the internal clock signal and a second timing for each of the address, the command and the write data to be changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.